This application is related to our patent application entitled xe2x80x9cMETHOD AND APPARATUS FOR EXHAUSTIVELY TESTING INTERACTIONS AMONG MULTIPLE PROCESSORSxe2x80x9d, filed Sep. 17, 1998, now U.S. Pat. No. 6,249,880, with Ser. No. 09/156,378, and assigned to the assignee hereof.
This application is related to our patent application entitled xe2x80x9cCALENDAR CLOCK CACHING IN A MULTIPROCESSOR DATA PROCESSING SYSTEMxe2x80x9d, filed Sep. 17, 1998, now U.S. Pat. No. 6,052,700, with Ser. No. 09/156,104, and assigned to the assignee hereof.
This application is related to our patent application entitled xe2x80x9cDATA PROCESSING SYSTEM PROCESSOR DELAY INSTRUCTIONxe2x80x9d, filed Sep. 17, 1998, now U.S. Pat. No. 6,230,263 with Ser. No. 09/156,376, and assigned to the assignee hereof.
The present invention generally relates to multiprocessing computer systems, and more specifically to dynamically modifying the tracing of internal processor signals during execution.
It has become increasingly difficult to determine what exactly a processor in a data processing system is doing at a low level. In particular, it has become extremely difficult to determine the intermediate states and operands in a processor during execution. There are a number of reasons for this problem. One reason is that processor speeds have increased to such an extent that equipment to monitor processor signals has failed to keep up with the increased processor speeds. Indeed, a doubling of processor speed results in much more than a doubling of test equipment costs to record internal processor states during processor execution.
One prior art solution to determining machine states, state transitions, and intermediate operands was to attach monitor probes to the various components and to record the signals generated by these components. This has become increasingly impossible to do as the level of integration has increased. While it was possible to attach probes to component outputs when the components comprised circuit boards, it is not possible when entire processors are incorporated on a single integrated circuit, along with their cache memories. It is even worse, when multiple processors are integrated on a single IC.
One prior art solution to determining machine states and state transitions is through the use of SCAN. Using SCAN, a known pattern of states can be loaded into a processor. The processor then executes one or two instructions. The states of the various memory elements in the processor are then unloaded from the processor and compared with their expected values. This type of functional testing is becoming common for high-end microprocessors. Unfortunately, it does not lend itself to exhaustively testing the interactions among multiple processors. One reason for this is that a processor under the control of SCAN typically only executes for one or two instruction cycles, before the SCAN latches are unloaded, and another set of values loaded. The result of this is that SCAN is extremely slow, especially in comparison to the speed of modern processors. This significantly reduces the amount of testing that can be realistically done with SCAN. Secondly, there is no readily apparent mechanism available to test multiple processor at the same time, and more importantly to vary the start times of each of the multiple processors being tested together.
In the past, it has been sometimes been possible to run enough signals out of a processor that the states and state transitions being tested can be monitored by test equipment. One problem with this method of testing is that it is a manual and error prone process. Just as important, this method is fast becoming less and less possible as more and more functionality is embedded on single chips. Pin-count has become a major concern, and it has become increasingly unlikely that precious external pins can be dedicated for the sort of interprocessor state testing described above. Also, this requires that signals be driven to the outside of an integrated circuit, which often has significant adverse performance impacts.
Another problem is that much of this prior art testing and tracing is static. The paths are laid out in silicon. Invariably, the signals that need to be traced or monitored to solve a given problem are not the signals that the designers expected to need for debugging.
Solving internal processor problems would be significantly eased if a mechanism were available to dynamically and selectively trace the various internal signals and operands in a processor and to record these dynamically selected signals and operands for later retrieval and analysis. This would significantly aid in solving processor problems.